In integrated circuit processing, it is well known to form a low resistivity silicide layer over a region of silicon or polysilicon. It is sometimes desirable to form a continuous silicide layer over both a polysilicon line and an adjacent silicon region to short the line and the region together, while insulating the silicide layer from other polysilicon lines and other silicon regions.
A silicide is generally formed by depositing a layer of refractory metal, such as titanium, cobalt, tungsten, platinum, or tantalum, on an exposed silicon (or polysilicon) surface of a wafer and then heating the wafer to alloy the silicon surface with the refractory metal to form a silicide (e.g., TiSi.sub.2). Since the deposited refractory metal does not alloy with oxide, the layer of pure refractory metal may be easily removed from over any oxide portions on the wafer using a selective etching solution. Thus, forming self-aligned silicide (called salicide) is a very effective tool to improve the performance of integrated circuit components.
In order to prevent a silicide layer from undesireably shorting together a polysilicon line and an adjacent single crystal silicon region, the polysilicon line must be separated from the silicon region by an oxide portion. Such an oxide portion may take the form of an oxide spacer formed along a side edge of the polysilicon line. After a refractory metal is deposited on the polysilicon, silicon region, and oxide spacer, the wafer is heated. A silicide is only formed over the polysilicon and silicon region, and no silicide is formed over the oxide spacers. The refractory metal is etched away from over the oxide spacers, and the now low resistivity polysilicon line remains insulated from the silicon region.
When desiring to form a continuous silicide layer over both a polysilicon line and an adjacent silicon region (such as a source, drain, or base region), a portion of the oxide spacer separating the polysilicon line from the silicon region must be removed. It has been discovered by the Applicants that in certain masking and etching processes for removing exposed portions of the oxide spacers from polysilicon lines, the oxide etching solution undesirably tunnels along oxide spacers under the photoresist mask. This tunneling can reach portions of other oxide spacers which are not desired to be etched away. This unintentional etching of an oxide spacer causes a silicide to form in the voids of the oxide spacer during the silicide formation process and undesirably forms a short under the oxide spacer. The silicide portions being shorted together may be overlying a base and an emitter region of a bipolar transistor, thus shorting these regions together and rendering the transistor inoperable. An example of this is described later with respect to FIGS. 8 and 9. Applicant's discovery of this reason for failure of a transistor is nonobvious. Such a situation may also occur for CMOS transistors where the silicide formed over a polysilicon gate shorts to a silicide portion formed over the source or drain region.
What is needed is an improved process to prevent tunneling of the oxide etching solution under a photoresist mask from damaging an oxide spacer. One such process to be improved is that described in U.S. Pat. No. 5,139,961, assigned to the present assignee and incorporated herein by reference.